The invention is directed to a method for data protection in the transmission of serial data bit sequences, by use of data block protection information generated with the assistance of cyclical binary codes formed in a coder unit at the transmission and a corresponding coder unit at the reception side.
In information technology, the data protection of serial data bit sequences to be transmitted is predominantly carried out by block protection methods with cyclical binary codes. The employment of cyclical binary codes in block protection methods principally serves the purpose of an effective error detection in the transmission of serial data bit sequences via transmission links. The periodical "Elektronik", 1976, Pages 55-59, discloses such a data protection method with cyclical binary codes, as well as circuits for realizing the method. The data block protection information for a block, or for a defined plurality of data bits to be transmitted, is identified by the division of a message polynomial representing the data bit sequence by a generator polynomial representing the cyclical binary code. The division remainder is serially attached to the data bit sequence at the transmission side as a code word signifying data block protection information, and is transmitted with the data. At the receiving side, the block protection information code word is identified from the received data bit sequence, on the basis of the known data block protection method, and is compared to data block protection information generated at the transmission side and transmitted with the data. Given faultless transmission of the data bit sequence, the two data block protection information code words coincide; given faulty transmission, the presence of an error can be recognized on the basis of the result by a noncomparison, and conclusions can be drawn regarding the type of error such as, for example, a single error, a double error or an error burst. The data block protection information is generated in a coder unit composed of a plurality of registers connected in sequence following one another. Every register has a polynomial ordinal number corresponding to the binary code polynomial allocated to it, in ascending sequence, whereby every register represents one member of the binary code polynomial.
A binary division element, constructed by an exclusive-OR or a half-adder circuit, is inserted following those registers which represent a member of the binary code polynomial provided with terms. One input and the outputs of the logic elements are respectively connected to the preceding and the following registers. The output of the register provided with the highest polynomial ordinal number is connected to the input of a further division element. The data bit sequence to be protected is connected to the second input of this further division element. The output of the further division element is connected to all of the second inputs of the first series of division elements, as well as to the input of the register provided with the lowest polynomial ordinal number. The clocking of the registers is synchronized with the bit clock of the data bit sequence.
This method is preferably realized in coder units which are formed of a plurality of discrete circuits or which are implemented in a mask-programmable, integrated circuit, which can be referred to as a "customized" circuit. Computer-controlled coder units can also be utilized at lower transmission rates. The steadily increasing quantities of data to be transmitted in the shortest possible time in communications technology leads to a constant increase in the transmission rates, whereby a power-consumption-intensive, discrete circuit technology is required and implementation in a mask-programmable integrated circuit is now only possible with certain limitations, and the realization in a computer-controlled coder unit is no longer possible.